1. Field of the Invention
The present invention relates to a scan-path flip-flop circuit for an integrated circuit memory.
2. Description of the Related Art
Japanese Patent Publication 2001-183424 discloses an integrated circuit in which a standard cell and a custom cell are combined. A scan-mode test circuit is provided in the custom cell for testing the boundary between the two cells. The test circuit is comprised of logic gates whose inputs are connected to the standard cell and whose outputs are connected through return paths to the standard cell. A test pattern is applied to each logic gate for testing a border area between the two cells. However, if the disclosed test circuit is employed for testing data input terminals of an integrated circuit memory, a dedicated set of logic gates and a dedicated set of test terminals would be provided to observe different states of each logic gate. The test pattern required for testing the data input terminals is a pattern capable of verifying all possible states of each logic gate. Thus, the test pattern would become long and impracticable.
Japanese Patent Publication 2001-142736 discloses an integrated circuit incorporating two groups of double-latch scan-path flip-flops, with one group being located between a first user logic and a macro cell and the other being located between a second user logic and the macro cell. The two groups of double-latch flip-flops are connected to form a scan path. The double-latch flip-flops hold a test pattern for testing the macro cell and a test pattern for testing the user logic. These test patterns are combined together to permit testing to be made simultaneously on the macro cell and the user logic. The macro cell is tested by shifting a normal-mode data signal through the scan-path flip-flops. Using a scan test, a failure which would occur between a data input terminal and a data output terminal is detected.
However, the scan-path flip-flops are only used for testing the macro cell and the user logic circuits. These flip-flops are thus dedicated for testing, and not used for user logic.
Therefore, there is a need to provide a scan-path flip-flop circuit capable of testing terminals of an integrated circuit with a short test pattern and capable of being efficiently used for purposes other than testing.